1. Technical Field
The present invention relates generally to integrated circuit design software and in particular to design checking functionality within comprehensive integrated circuit design systems. Still more particularly, the present invention relates to enabling layout design checking capabilities to efficiently handle multiple physical layouts for a given schematic cell.
2. Description of the Related Art
Integrated circuits are generally designed as a conglomeration of xe2x80x9ccells,xe2x80x9d logical subdivisions of the total circuit design which may be nested hierarchically so that top level cells are subdivided into other cells, which may be further subdivided in lower levels. Cells at any level may be formed as a composite of lower level cells and subcells. As a simple example, a particular integrated circuit may include a clock generator for generating multi-phase clock signals, with the clock generator being formed from a plurality of inverters and NAND or NOR gates. The clock generator may be treated logically as a single cell at one level, subdivided into separate cells for the inverters and gates at the next lower level.
Integrated circuit design software typically includes both electrical circuit schematic layout and physical layout capabilities operating in a coordinated manner. Generally included are checking functions for checking the schematic design and circuit operation, as well as the physical layout design. For checking physical layouts, hierarchical checking techniques would be preferable to conventional flat checking techniques. In flat checking, each cell is checked individually for compliance with process restrictions and design rules (such as contact spacing and/or enclosure rules) regardless of the number of times which the same layout design is reused in different locations. In hierarchical checking, however, a specific layout design utilized in multiple locations is checked internally only once for compliance with design rules, and is then merely checked for proper connections at subsequent locations. For self-evident reasons, hierarchical checking allows greatly improved checking times and memory usage over conventional flat checking, but at the expense of some restrictions and drawbacks.
One restriction necessary to enable hierarchical checking is strict conformity of physical layouts in every instance of a given cell to a defined physical layout for the cell, allowing a check of the defined physical layout for the cell to serve as a check for each cell instance. This may be ensured, for example, by unique naming of each physical layout, requiring that the physical layout design of any distinct layout cellxe2x80x94including physical layout variations of the same schematic layout cellxe2x80x94be uniquely named. Such variations of the physical layout design for a cell may be required, for instance, due to the different layout requirements from neighboring cells at different locationsxe2x80x94that is, required connections to neighboring cells may compel reversal of the physical layout or alteration of the different number of data input or output signals.
Hierarchical checking of a layout cell which has the same name as the schematic in one location but a different layout cell name (or another different attribute) in another location may result in a false error. Where the schematic cell name does not match the layout cell name, checking functionality will place the schematic cell name into an xe2x80x9cexplode list,xe2x80x9d causing all occurrences of that cell to be exploded into the detailed layout and checked flat at the transistor or device level. In the case of a frequently used cell such as a clock driver, hundreds or even thousands of instances of the standard layout cellxe2x80x94the layout cell with the name matching the corresponding schematic cell namexe2x80x94may exist. Exploding all of those instances due to a few instances of a special layout cell also corresponding to the schematic cell results in much unnecessary checking, increasing the run time and memory usage and also resulting in poor diagnostics.
An alternative to exploding every instance of the mismatched cell is to copy the original schematic cell to the name of the new or special layout cell. However, this forces schematic changes late in the design cycle and necessitates rerunning of many schematic checking tools, timing tools, test generation tools, etc. since normally the schematic design and schematic checking are all completed before beginning layout. Normal design methodology would require that many tools be run against the schematic before layout is even started, assuring that the circuit design implements the correct function, generating early timing rules and test generation rules, performing electrical checks, and the like. Once checked, the schematic is then xe2x80x9cfrozenxe2x80x9d and layout begins. Since the need for an alternative layout cell corresponding to a given schematic may not be discovered until layout is in progress, introduction of a new schematic cell named to match the alternative layout would necessitate rerunning of all schematic checking tools to satisfy stringent design checking requirements normally applied. The use of a separate schematic for the alternative layout also increases data volume and, in the case of an updated to the original schematic, allows the possibility of overlooking the new, differently-named version of the schematic and failure to make the required change to that cell as well as the original.
A third alternative is to allow a list of layout cell names to be attached to a schematic cell, where each of the layout cells is a different physical layout of the same electrical circuit. However, it frequently occurs that initially only one layout cell is envisioned for a particular schematic. Later, in the course of layout, it may be discovered that two or more layout designs may be required for a given cell to allow for different boundary conditions within different instances of the layout cell as described above, for example. A change to the schematic cell to add the name of the new layout cell would then be necessary. As noted above, it is exceedingly inconvenient and time consuming to modify the schematic after layout has begun since any modificationxe2x80x94even merely adding a new layout cell name to the list of layout designs corresponding to a given schematicxe2x80x94changes audit records and forces tools to be rerun to satisfy the stringent design checking procedures typically employed in contemporary integrated circuit design.
The related application describes a solution in which essentially all layout cells having a cell name which does not match the corresponding schematic cell name are automatically xe2x80x9cexplodedxe2x80x9d by the checking tool for flat checking, while hierarchical checking is preserved for those layout cell instances with a cell name which matches the corresponding schematic. However, this imposes certain drawbacks: first, many more devices are xe2x80x9cpushedxe2x80x9d down to a lower level, increasing memory requirements and run times for checking; and second, in the case of an actual layout error, poorer diagnostic messages result, making it much more difficult and time-consuming to find and correct layout errors.
It would be desirable, therefore, to allow layout design checking functionality to efficiently handle multiple physical layouts for a given schematic cell within an integrated circuit design, even when the need for one or more alternative layouts for a particular cell is not identified until layout is in progress.
It is therefore one object of the present invention to provide improved integrated circuit design software.
It is another object of the present invention to provide improved design checking functionality within comprehensive integrated circuit design systems.
It is yet another object of the present invention to enable layout design checking capabilities to efficiently handle multiple physical layouts for a given schematic cell.
The foregoing objects are achieved as is now described. An EQUATE property is introduced into the layout cell data for a layout design to identify the schematic to which the layout design corresponds. Rather than exploding the layout cell down to the next level for flat checking because the equivalent schematic is not known, the layout cell instances may then be checked hierarchically, with one instance checked internally for compliance with design rules and the like while the remaining instances are merely checked for proper connection to neighboring cells. New layout cell designs may therefore be created as the need arises during layout without requring schematic checking tools to be rerun.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.